High yield, low variability – Employing silicon CMOS technology for the realization of spin qubits

• Applicants: Professor Dr. Joachim Knoch; Dr. Lars Reiner Schreiber
• Subject Area: Electronic Semiconductors, Components and Circuits, Integrated Systems, Sensor Technology, Theoretical Electrical Engineering ; Experimental Condensed Matter Physics
• Term: from 2019 to 2023
• Project identifier: Deutsche Forschungsgemeinschaft (DFG) - Project number 421769186

In recent years, all building blocks for quantum computation using spin qubits were demonstrated in electrostatically defined spin qubits based on e.g. GaAs or Si. Remaining manipulation infidelities are tolerable by using a surface code which requires a large number of physical qubits. As a result, the feasibility of a spin qubit quantum computer is directly related to the scalability of the system. However, even state-of-the-art qubit realizations rely on a rather immature fabrication technology with very low yield and large device-to-device variability. Furthermore, complex multi-layer gate patterns will be required to improve the confinement potentials and to realize new functionalities e.g. a quantum bus. In the current project a qubit technology will be developed that is based on fabrication techniques derived from industrial silicon CMOS technology ensuring scalability and a high yield of our approach. Due to the low-temperature operation and in order to guarantee tunability of the qubits a very large number of nanoscale gate electrodes will be realized on top of a semiconductor heterostructure in which the single electron spin representing qubits will be defined electrostatically. For the realization of these gate structures we will use the so-called (multiple) spacer process which not only avoids the need for highly sophisticated nanolithography (such as electron-beam lithography). More importantly, it significantly reduces the device-to-device variability. This strongly increases the yield and in addition might even allow a reduction of the total number of gates necessary to electrostatically tune the individual qubits. The fabrication will be carried out with the lowest possible ther-mal budget such that the impact on the heterostructure is minimized (e.g. no reduction of valley splitting in Si/SiGe quantum wells) and that the developed technology can be used for different substrates such as GaAs/AlGaAs.Throughout the project MBE-grown Si/SiGe multi-quantum dot samples will be fabricated. The gate-tunability of the quantum dots, the electrostatic noise and the valley splitting are determined by transport measurements at ~20 mK. Qubit functionality such as charge-readout by an adjacent read-out quantum dot and spin-to-charge conversion will be demonstrated. Within the project we aim at extending the number of quantum dots to 40 without losing tunability and functionality of each quantum dot. The multi-quantum dot samples allow mapping the valley splitting variability over a large area. Combining the development of appropriate fabrication technologies to facilitate groundbreaking work on multi quantum dot/qubit devices our approach has the potential to provide highly relevant contributions to the science and technology of the field. Furthermore, since the technology devel-opment will be as close as possible to current industrial processes it may help accelerating the realization of future quantum information processors.

• DFG Programme: Research Grants
• Cooperation Partner: Professor Dr. Dominique Bougeard