NeuroTest: Testing Solutions for Neuromorphic Circuits and Architectures

• Antragsteller: Professor Mehdi B. Tahoori, Ph.D.
• Fachliche Zuordnung: Rechnerarchitektur, eingebettete und massiv parallele Systeme ; Elektronische Halbleiter, Bauelemente und Schaltungen, Integrierte Systeme, Sensorik, Theoretische Elektrotechnik
• Förderung: Förderung von 2019 bis 2024
• Projektkennung: Deutsche Forschungsgemeinschaft (DFG) - Projektnummer 429238884

• Erstellungsjahr: 2024

Zusammenfassung der Projektergebnisse

Our research is structured into three interlinked work packages (WPs), each targeting a key dimension of the testing problem: WP1 – Fault Modeling and Failure Analysis. This work package focused on modeling the faults that arise in neuromorphic circuits from both structural (circuit-level) and functional (network-level) perspectives. • We introduced cross-layer test flows that distinguish between algorithmic errors and hardware faults by analyzing whether faults violate a defined inference accuracy threshold. Only functionally significant faults are detected, reducing unnecessary test cost. • Further Papers focused on CiM-specific defect modeling in NVM technologies. We identified defects in STT-MRAM that lead to faulty logic operations in in-memory computing and neuromorphic tasks, including threshold failures in analog-like behavior. • These efforts laid the groundwork for fault models that are aware of neuromorphic behavior, implementation technologies, and their system-level impact. WP2 – Test Pattern Generation. In WP2, we developed novel test generation approaches that are scalable and cognizant of neural network behavior. • We proposed a training data-based test generation flow that selects minimal but effective input patterns to achieve up to 100% fault coverage using only 0.128% of the dataset, significantly reducing test effort. • We developed a heuristic ATPG for detecting neuron-level stuck-at faults using input patterns that cause class label deviations, along with K-means clustering to reduce the test set size. • Then we introduced a compressed test generation method, representing all test patterns as linear combinations of basis patterns, achieving 99.99% coverage with a compression ratio up to 307×. • Collectively, these methods demonstrate effective TPG under accuracy constraints, with a focus on reducing test size, complexity, and application cost. WP3 – Design-for-Test and Diagnosis. Finally, WP3 addressed how to enable practical testability in neuromorphic circuits through architectural and technological enhancements. • Some of our papers indirectly contributed by revealing test-access limitations in crossbar arrays and suggesting resistive test optimization techniques such as resistance trimming and March-based sequences. • WP3 builds on these findings to explore novel DfT strategies for synaptic arrays, improving observability and controllability while avoiding digital scan-based DfT assumptions. • This included identifying algorithmic nodes (e.g., specific layers in DNNs) for instrumentation and investigating how fault tolerance margins can guide selective testing and access point insertion. The NeuroTest project delivered the comprehensive cross-layer methodology for testing neuromorphic computing systems, spanning fault modeling, test generation, and DfT. It paves the way for technology-aware, cost-effective, and functionally relevant test solutions in future AI hardware platforms, especially those based on emerging NVM technologies and neuromorphic architectures.

Projektbezogene Publikationen (Auswahl)

• Testing of Neuromorphic Circuits: Structural vs Functional. 2019 IEEE International Test Conference (ITC), 1-10. IEEE.
  Gebregiorgis, Anteneh & Tahoori, Mehdi B.
  
• Defect Characterization and Test Generation for Spintronic-based Compute-In-Memory. 2020 IEEE European Test Symposium (ETS), 1-6. IEEE.
  Nair, Sarath Mohanachandran; Munch, Christopher & Tahoori, Mehdi B.
  
• Defect Characterization of Spintronic-based Neuromorphic Circuits. 2020 IEEE 26th International Symposium on On-Line Testing and Robust System Design (IOLTS), 1-4. IEEE.
  Munch, Christopher & Tahoori, Mehdi B.
  
• Analyzing and Mitigating Sensing Failures in Spintronic-based Computing in Memory. 2021 IEEE International Test Conference (ITC), 268-277. IEEE.
  Mayahinia, Mahta; Munch, Christopher & Tahoori, Mehdi B.
  
• Testing Resistive Memory based Neuromorphic Architectures using Reference Trimming. 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1592-1595. IEEE.
  Munch, Christopher & Tahoori, Mehdi B.
  
• Compact Functional Test Generation for Memristive Deep Learning Implementations using Approximate Gradient Ranking. 2022 IEEE International Test Conference (ITC), 239-248. IEEE.
  Ahmed, Soyed Tuhin & Tahoori, Mehdi B.
  
• PVT Analysis for RRAM and STT-MRAM-based Logic Computation-in-Memory. 2022 IEEE European Test Symposium (ETS), 1-6. IEEE.
  Fieback, Moritz; Munch, Christopher; Gebregiorgis, Anteneh; Medeiros, Guilherme Cardoso; Taouil, Mottaqiallah; Hamdioui, Said & Tahoori, Mehdi
  
• Automatic Test Pattern Generation and Compaction for Deep Neural Networks. Proceedings of the 28th Asia and South Pacific Design Automation Conference, 436-441. ACM.
  Moussa, Dina; Hefenbrock, Michael; Münch, Christopher & Tahoori, Mehdi
  
• Compact Test Pattern Generation For Multiple Faults In Deep Neural Networks. 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-2. IEEE.
  Moussa, Dina A.; Hefenbrock, Michael & Tahoori, Mehdi
  
• Compressed Test Pattern Generation for Deep Neural Networks. IEEE Transactions on Computers, 74(1), 307-315.
  Moussa, Dina A.; Hefenbrock, Michael & Tahoori, Mehdi