Dual-Quantization Multibit Delta-Sigma Modulators with high internal resolution – DuQ2.0

• Applicant: Professor Dr.-Ing. Maurits Ortmanns
• Subject Area: Electronic Semiconductors, Components and Circuits, Integrated Systems, Sensor Technology, Theoretical Electrical Engineering
• Term: since 2020
• Project identifier: Deutsche Forschungsgemeinschaft (DFG) - Project number 433735880

Continuous-time (CT) Delta-Sigma (DS) Analog-to-Digital Converters (ADC) offer great advantages concerning speed, drivability and power efficiency. For wideband applications, the useable oversampling ratio is restricted; thus, to maintain good resolution either the internal bitwidth or the loop-filter order of the DS modulator must be significantly increased. For single-loop implementations, the order is restricted due to stability. While higher internal bitwidth is beneficial for stability and resolution, its implementation complexity raises exponentially with the number of bits. This is especially true for the feedback Digital-to-Analog Converter (DAC), which needs a linearity at least as good as that of the overall DS ADC. In the first project phase, solution were to be found to de-couple the bitwidth and thus complexity of a high internal quantizer resolution from that of the employed DAC. One concept investigated dual-quantization based on a multi-stage noise-shaping (MASH) digital DSM (DDSM) in the feedback of a main DSM; thereby, the MASH concept allows higher-order DDSM noise-shaping order without suffering from stability issues. Moreover, it allows to use intrinsically linear 1..1.5-bit DACs in the first stage of the DDSM, where the signal is processed, while a highly-multibit DAC can be employed in higher DDSM MASH stages without suffering from DAC non-linearity, because it majorly processes quantization noise. Also, the first project phase investigated a dual quantization by means of a high-resolution internal quantizer, where only a part of its bits is used as (in-time) feedback bits, while least significant bits are either processed later in time or only in the digital domain. In continuation, we aim to work on SMASH DDSM in the feedback of a main DSM for the purpose of dual quantization. While SMASH also allows higher order noise-shaping, separation of the 1.5-bit first stage for signal and (non-linear) multibit second stage for quantization noise processing, its distinct advantage is that it omits a reconstruction filter. Thus, it promises lower complexity and matching requirements. The SMASH DDSM will be compared to the already found architectures to digest the most promising one. Furthermore, 1.5-bit DACs are known to be intrinsically linear in the state of the art. But this is only true for static non-linearity. When it comes to dynamic non-linearity, it generates both even and odd harmonics from a capacitive error charge associated with the switching of a current-steering DAC-cell. We will investigate analog solutions to counteract this by shielding the parasitic capacitance as well as by an error control loop. Finally, the continuation phase aims for a circuit implementation to validate the most promising dual quantization architectures in a modern CMOS technology.

• DFG Programme: Research Grants