Methodology, Algorithms, and Framework for Hardware Design Understanding

• Applicant: Professor Dr.-Ing. Görschwin Fey
• Subject Area: Computer Architecture, Embedded and Massively Parallel Systems
• Term: from 2020 to 2024
• Project identifier: Deutsche Forschungsgemeinschaft (DFG) - Project number 450387614

• Final Report Year: 2024

Final Report Abstract

Understanding a given digital system design one is unfamiliar with is at least as hard as implementing it. Particularly, this holds for systems designed in large projects where no single person knows all the details, legacy components with poor or outdated documentation are reused, and team members change regularly. Designers then try to understand the inner logic of the design using various sources – informal discussions with team members, textual information like documents for requirements and specifications, and review as well as execution of source code and test cases. This project created a tool to support designers in understanding the source code of a system design at the Register Transfer Level (RTL). The main focus was on techniques and algorithms known from security analysis and their application for design understanding, investigating the first steps towards advanced user interfaces, providing benchmarking cases, and open-sourcing the resulting implementation. The tool DuRTL is now available in its first release. Moreover, the recently drastically increased capabilities of Large Language Models (LLMs) directly relate to the theme of the project, so initial steps toward assessing their capabilities have been made.

Link to the final report

https://doi.org/10.15480/882.15188

Publications

• Design Understanding: Identifying Instruction Pipelines in Hardware Designs. 2022 11th International Conference on Modern Circuits and Systems Technologies (MOCAST), 1-6. IEEE.
  Schammer, Lutz; Runge, Jan; Klimach, Paula & Fey, Goerschwin
  
• DuRTL – a tool for design understanding of RTL code, 2024.
  Gianluca Martino, Lutz Schammer & Goerschwin Fey
  
• Evaluating the Performance of Large Language Models for Design Validation. 2024 IEEE 37th International System-on-Chip Conference (SOCC), 1-6. IEEE.
  Rahman, Abdur & Fey, Goerschwin
  
• Usage Driven Relevance Analysis for IP Cores. 2024 IEEE 37th International System-on-Chip Conference (SOCC), 1-6. IEEE.
  Schammer, Lutz; Martino, Gianluca & Fey, Goerschwin