Technology-aware 3D interconnect architectures for heterogeneous SoCs manufactured in monolithic 3D integration

• Applicants: Professor Dr. Alberto Garcia-Ortiz; Professor Dr.-Ing. Thilo Pionteck
• Subject Area: Computer Architecture, Embedded and Massively Parallel Systems
• Term: since 2021
• Project identifier: Deutsche Forschungsgemeinschaft (DFG) - Project number 466544818

Monolithic 3D integration (M3D) is a disruptive technology for the design of 3D System-on-Chips. In contrast to more conventional 3D integration schemes, M3D permits a very dense integration of vertical interconnects between neighboring tiers. Together with extrinsic heterogeneity, i.e., the combination of tiers with different electrical characteristics, unprecedented opportunities for new architectural designs and extended system functionalities arise. These benefits have been proven by numerous works addressing processing elements and memories; yet, for on-chip communication architectures such as Network-on-Chips, only few related works exist. Further on, these works often neglect the significant impact of intrinsic heterogeneity caused by monolithic fabrication, such as process-related transistor degradations on higher tiers, interconnect degradations on lower tiers, or the non-uniform distribution of routing resources among tiers. Finally, previous works primarily exploit wire length reduction in 3D, yet do not consider the extended micro- and macroarchitectural design space. We want to address all of these shortcomings by analyzing how the characteristics of monolithic 3D integration affect the design of the microarchitecture of individual network components, and the architecture of the communication infrastructure. Furthermore, we will analyze the impact of these modifications and extended design options on the overall system architecture. The project will provide four specific contributions to the scientific community: 1) It will provide systematic design guidelines and a set of architectural templates for optimized 3D interconnect architectures addressing extrinsic and intrinsic heterogeneity; 2) It will provide models for formulating Network-on-Chip topology synthesis as an optimization problem; 3) It will provide a toolset for supporting a systematic design space exploration, which accounts for all relevant M3D technology characteristics;4) It will demonstrate the optimization potential by means of two demonstrators, a Vision-System-on-Chip and a multiprocessor system.The main outcome of this project will be a deeper understanding on how the disruptive characteristics of Monolithic 3D integration can be exploited for improving the interconnect architecture in 3D integrated circuits. This allows for the design of optimized systems, not supported by current design concepts.

• DFG Programme: Research Grants