DART: Design Automation for Reconfigurable Transistors

• Applicant: Professor Dr. Akash Kumar
• Subject Area: Computer Architecture, Embedded and Massively Parallel Systems
• Term: since 2022
• Project identifier: Deutsche Forschungsgemeinschaft (DFG) - Project number 500109949

Shrinking feature sizes has long been a major factor to improve CMOS circuit performance. This led to zero-effort performance gains inelectronic circuit architecture in the past. By approaching the power wall for current CMOS scaling factors we see an increased need forthermal management and the need to employ dark silicon schemes to provide both the necessary performance and utility at the same time.In this project, we investigate the possibilities for reconfigurable transistors to reshape electronic circuit design to provide a higherfunctional density while maintaining sufficiently low power consumption. To achieve this, we exploit unique properties likemultiple gates per transistor next to their reconfigurability. We focus on a model-based approach to design a new standard cell library by using probabilistic model checking. For this we extend a model checker to design and verify new cells. In close collaboration with nanomaterials research we refine our models to fit the projections and laboratory implementations of emerging technology devices.The new standard cell library will not only map current CMOS cell designs to new technology but will also cover new cells with a highercomplexity and thus functionality. We expect that this will put greater load on to the logic synthesis that is responsible for standard cell selection.We also take the logic synthesis flow into account. While an unmodified EDA flow will produce preliminary results, we expect thatmodifications to technology mapping that take circuit reconfigurability and different cell properties into account will be needed to take full advantage of the new possibilities. Close communication between the model-approach and the EDA flow may also make a logic synthesis approach feasible that circumvents the limitations of current standard-cell-based EDA approaches.We design a comprehensive testing and benchmarking framework. This allows us to not only compare our new design flow against a CMOS EDA flow, but also allows us to track our own progress in standard cell design and modifications to the EDA flow.The applicant has extensive knowledge and research experience in reconfigurable architecture designs. For example, he has recentlyproposed novel approaches to compute the routing for FPGA-based systems and successfully tackled the problem of floorplanningruntime-reconfigurable design to increase design utility and density. He has also done significant research in improving EDA for emerging nanotechnologies. Various tool flows have been released as open-source for the benefit of the research community. Most of the work has been published at top conference venues like DAC, DATE and ICCAD, and reputed IEEE transactions. We therefore see significant potential for further high-profile publications.

• DFG Programme: Research Grants