CXL-Bridge: CXL controllers for heterogeneous memory architectures

• Applicant: Professor Dr.-Ing. Pramod Bhatotia
• Subject Area: Security and Dependability, Operating-, Communication- and Distributed Systems ; Computer Architecture, Embedded and Massively Parallel Systems
• Term: since 2022
• Project identifier: Deutsche Forschungsgemeinschaft (DFG) - Project number 501680474

CXL is a rapidly emerging interconnect technology that promises high-speed, rack-level communication between compute nodes and memory devices. By consolidating memory into shared pools and exposing them as physical ranges, CXL enables CPUs across machines to conveniently access vast memory resources using traditional load/store instructions. To ensure data coherence across shared memory, CXL specifies its own MESI-like cache-coherence protocol, offering an efficient and hardware-based solution to interact with remote memory. However, the CPU \textit{internal} cache-coherence protocols are tightly integrated with the memory subsystems of modern CPUs, tailored to their specific architectures and memory consistency models (MCMs). This tight coupling poses significant challenges in extending or inter-operating with other \textit{external} protocols, such as CXL, especially in heterogeneous systems where devices use diverse protocols and MCMs. In this research proposal, we strive to address the challenge of integrating CXL’s cache-coherence protocol with any vendor-specific protocols through the development of a novel CXL bridge generator. Our proposed system automatically synthesizes and verifies CXL bridges, enabling seamless interoperability between diverse compute nodes and other CXL devices without modifying the internal protocols. The generated bridges guarantee deadlock-free operation and adherence to the memory consistency models of both CXL and host systems, ensuring correctness and performance in heterogeneous environments. The tangible outcomes of this work include: (1) a compound coherence protocol framework for integrating heterogeneous CPU's and CXL memory systems; (2) a functional, end-to-end CXL bridge generator for synthesizing and evaluating protocol fusion; (3) an efficient verification framework tailored to hierarchical CXL systems ensuring safety and liveness properties of the generated bridges; and (4) a comprehensive performance analysis using Gem5 simulations, evaluating the performance of protocol fusion and our bridge designs.

• DFG Programme: Priority Programmes
• Subproject of: SPP 2377: Disruptive Main-Memory Technologies