HYPNOS - Co-Design of Persistent, Energy-efficient and High-speed Embedded Processor Systems with Hybrid Volatility Memory Organisation

• Applicants: Professor Dr.-Ing. Jürgen Teich; Dr.-Ing. Stefan Wildermann
• Subject Area: Computer Architecture, Embedded and Massively Parallel Systems ; Software Engineering and Programming Languages
• Term: since 2022
• Project identifier: Deutsche Forschungsgemeinschaft (DFG) - Project number 502213043

HYPNOS investigates the use of NVM technologies not only for main memory but also across the entire cache hierarchy and registers of modern embedded processors. It aims to optimize this hybrid-volatile memory hierarchy to provide high speed and low energy consumption for various embedded applications. At the same time, it ensures the persistence of data structures and processing states in a simple and efficient way. Fully non-volatile processors (NVPs) suffer from high write times as well as orders of magnitude lower NVM endurance than SRAM, prohibiting operation at GHz speeds. Moreover, existing NVM main memory computers suffer from the need of the programmer to explicitly persist data structures. HYPNOS (Named after the Greek god of sleep) systematically attacks this performance/endurance/programmability gap on the basis of CPU architectures with hybrid (mixed volatile/nonvolatile) caches as explored in the first phase. Investigations planned for the second phase include: a) Implementation of and compiler support for HW transactions in hybrid-volatile cache CPU architectures for failure atomicity in the multi-core context; b) Optimization of performance and energy consumption of hybrid cache architectures through introduction of program annotations ("hints") carrying information about read and write behaviour of statically analyzed and profiled data segments and using these inside the cache controllers of the hybrid cache architecture; c) "Volatility on demand" explores mechanisms to selectively avoid persisting all data and code during power failures. It includes software-defined volatility preferences, hardware techniques for crash consistency and consistent recovery, and strategies to optimize energy efficiency in intermittent computing. d) The concepts developed in a),b), and c) shall be systematically evaluated in terms of performance, energy consumption and backup and recovery times through extension of the gem5-based simulation platform. As applications, a focus will be put on IoT benchmarks and scenarios of energy scarcity, including sensor processing and embedded control applications.

• DFG Programme: Priority Programmes
• Subproject of: SPP 2377: Disruptive Main-Memory Technologies