Project Details
Projekt
Reconfigurable Architectures and Real-Time Systems Co-Design for Non-Volatile Main Memory (ARTS-NVM)
Subject Area
Data Management, Data-Intensive Systems, Computer Science Methods in Business Informatics
Term
since 2022
Project identifier
Deutsche Forschungsgemeinschaft (DFG) - Project number 502308721
Embedded system applications demand high computing performance at lower power consumption and increasingly large memory footprint. These, partly contradictory, constraints require new methodologies and/or new system architectures. Emerging non-volatile memories, a disruptive technology, offers a great potential to replace conventional DRAM and SRAM as main memory in such systems and also in reconfigurable fabrics as part of the same. However, besides potential advantages, there are also challenges to overcome in order to profit from NVMs new characteristics. This research project aims at developing NVM-based reconfigurable architectures and sound timing analyses that can safely utilize NVMs as main memory in real-time embedded systems and/or as reconfigurable fabrics by significantly improving the timing predictability and the quality of wear-leveling system routines. Although there have been various efforts in investigating disruptive design issues and worst-case timing analyses, their intersections cannot yet model, analyze or operate the system with NVMs in real-time systems at a level needed for safe operation in a wide range of embedded computing systems. With the further evolution of complex embedded system applications, large memory demand and low power consumption will be key in the near future, thereby demanding the need for NVM-friendly real-time operating systems and reconfigurable fabric. We have the following goals: i) Develop task models and timing-aware analysis to derive safe upper bounds on worst-case execution times and response times while accounting for prominent NVM-specific properties. ii) Develop architectural and system-level approaches to enhance the reliability and adaptability of NVM-based FPGAs by optimizing resource management and reconfiguration strategies while ensuring sustained performance requirements under the NVM constraints. iii) Enhance the system software to support NVM technologies by refining memory management, optimizing memory-mapped interfaces for controllers, and integrating monitoring facilities to improve online admission control. In literature proposed solutions have addressed some individual issues. However, considering their required time overhead, not sufficient attention has been paid to timing predictability. In addition, mitigating the stress of the NVM under given timing requirements is still an open question. In this project, we employ NVM as the main memory and as adaptive reconfigurable fabric. With this in mind from early design phases, we devise novel methodologies, analyses and optimization. We anticipate that the research results of our project will provide a new perspective on real-time embedded systems for disruptive memory technologies with timing-aware NVM-based reconfigurable architectures, and it will enrich the outreach of the scientific results of SPP 2377.
DFG Programme
Priority Programmes
Subproject of
SPP 2377:
Disruptive Main-Memory Technologies
