Project Details
Projekt
NIC-Level Co-Processors for Resilient Coded Networking and Computation
Subject Area
Security and Dependability, Operating-, Communication- and Distributed Systems
Electronic Semiconductors, Components and Circuits, Integrated Systems, Sensor Technology, Theoretical Electrical Engineering
Electronic Semiconductors, Components and Circuits, Integrated Systems, Sensor Technology, Theoretical Electrical Engineering
Term
since 2022
Project identifier
Deutsche Forschungsgemeinschaft (DFG) - Project number 503359370
Digital factories, or vehicular on-board networked IT infrastructure, e.g. of autonomous vehicles, are examples of an ever-growing number of cyber-physical networked systems where failures may cause material damage or may even endanger human lives. Reliable communication and computation under strict time constraints play a pivotal role in the next generation of networked system architectures. We anticipate requirements to transport multiple Gbit/s of data with mixed-critical time and safety profiles.Conventional Ethernet, while offering high data rates, was not designed to provide the quality of service and resilience levels that are important for such highly demanding application areas. Therefore, Time-Sensitive Networking (TSN) standards are being standardized for Ethernet-based time-sensitive and reliable services. One standardized solution for dependability in Ethernet is IEEE standard "802.1CB-Frame Replication and Elimination for Reliability" (FRER), which duplicates frames, resulting in a considerable overhead.In HyperNIC, we plan to investigate mechanisms and processing platforms that provide resilience efficiently and flexibly. We aim to design a novel class of Network Interface Cards (NICs) with processing capabilities that employ techniques such as Network Coding, low-latency retransmissions of coded packets, and fault-tolerant algorithms. A crucial aspect for providing resilient time-sensitive services is the availability of resilience mechanisms and high packet processing performance at the right location, thereby avoiding overloaded network and host components.Hardware offloading by NIC-level co-processors enables resilient, low-latency computation and can help to free scarce and expensive CPU resources. The investigated mechanisms for resilience will be modeled, implemented, and finally evaluated using real-world measurements. HyperNIC is a planned collaboration between Prof. Carle's research group, which has a strong background in the investigation and modeling of high-performance software packet processing systems, and the research group of Prof. Herkersdorf, which focuses on the design implementation, and analysis of high-performance co-processors. With the joint expertise of both research groups that have a history of successful collaborations, integration of hardware acceleration and software stack can be achieved, thereby addressing the SPP 2378 Resilient Worlds programme strategies "resilience meets silicon" as well as "resilience meets communication".
DFG Programme
Priority Programmes
