Joint Logic, Memory, and Routing Synthesis (B05)

• Subject Area: Electronic Semiconductors, Components and Circuits, Integrated Systems, Sensor Technology, Theoretical Electrical Engineering
• Term: since 2025
• Project identifier: Deutsche Forschungsgemeinschaft (DFG) - Project number 528378584

To assess more complex circuit and system options, an automated design environment is inevitable. Therefore, the central role of this project is to develop and maintain a simplified electronic design automation environment that will allow to design more complex systems in later phases. This is a crucial task since Active-3D eliminates boundaries between supply voltage and signals, memory, and logic and so forth, and therefore, new automated design strategies will be required and will need significant research and a continuous interaction with all other projects.

• DFG Programme: CRC/Transregios
• Subproject of: TRR 404: Next Generation Electronics with Active Devices in Three Dimensions (Active-3D)
• Applicant Institution: Technische Universität Dresden
• Co-Applicant Institution: Rheinisch-Westfälische Technische Hochschule Aachen
• Project Heads: Professor Dr.-Ing. Tobias Gemmeke; Professor Dr. Akash Kumar