Hierarchical Device Simulation and Modeling (C02)

• Subject Area: Computer Architecture, Embedded and Massively Parallel Systems
• Term: since 2025
• Project identifier: Deutsche Forschungsgemeinschaft (DFG) - Project number 528378584

In an early stage of the research, only small-scale demonstrations can be actually built in hardware. It is therefore essential to simulate the whole technology stack starting from the device function via the circuit up to the system level to do a well-founded performance assessment which is required in many projects of Research Area B. This also includes the exploration and characterization of advantageous basic logic cells that Area B will use to implement complex circuits and systems. In Research Area A advanced simulation techniques will be required to optimize the new devices. Supplying such possibilities to the different projects is the central role of this essential overarching project.

• DFG Programme: CRC/Transregios
• Subproject of: TRR 404: Next Generation Electronics with Active Devices in Three Dimensions (Active-3D)
• Applicant Institution: Technische Universität Dresden
• Co-Applicant Institution: Rheinisch-Westfälische Technische Hochschule Aachen
• Project Heads: Professor Dr.-Ing. Christoph Jungemann; Dr.-Ing. Stephan Menzel