High-Bandwidth and High-Sampling Rate Orthogonal Sampling-Based DAC using Low-Bandwidth Electronics (HighDAC)

• Applicants: Professor Dr.-Ing. Vadim Issakov; Professor Dr. Thomas Schneider
• Subject Area: Electronic Semiconductors, Components and Circuits, Integrated Systems, Sensor Technology, Theoretical Electrical Engineering
• Term: since 2025
• Project identifier: Deutsche Forschungsgemeinschaft (DFG) - Project number 556011446

This is the fully revised version of the rejected project: HighDAC. We have better described the background of our new method for signal processing and we have included a detailed description of sinc-pulse sequences (SPS). Additionally, we will use a 22 nm CMOS technology for chip fabrication. To save chip space and costs, we have a commitment from GlobalFoundries to reduce the price for fabrication by half and additionally, we will not integrate the low-bandwidth DAC on the chip. Instead, we will use commercial DAC (Evaluation kit RFSoC ZCU216). Additionally, to show the potential of our new method, we will integrate three stages on the chip to achieve 27 times the bandwidth and sampling rate (135 GHz and 270 GS/s) from the 5 GHz and 10 GS/s commercial DACs. Digital-to-analog converters (DAC) and arbitrary waveform generators (AWG) with high sampling rate and bandwidth are essential for many different applications from digital radar, via sensors to communications. In the field of communications, for instance, the unprecedented success of electronic integration, together with massive parallelization has enabled new applications like video streaming, online gaming, industry X.0 and autonomous driving. However, to keep pace with the ever increasing data rates in future applications, new approaches for AWGs and DACs are required. In HighDAC we will investigate the possibilities and limits of a new method to generate high bandwidth, high sampling rate arbitrary signals by means of realizing a System-on-Chip (SoC) composed of sub-blocks having low bandwidth and low sampling rate. This is achieved using the novel approach of orthogonal sampling by sinc pulse sequences (SPS). We aim to show that this new method enables implementing integrated DACs with sampling rates and bandwidths far beyond the state of the art (>>100 GHz). To investigate the potential of the method, we aim to demonstrate the realization of a hybrid system, which acts as a DAC having 270 GS/s (135 GHz analog bandwidth) with an effective number of bit (ENOB) of 7. This system shall be composed of “simpler” integrated DACs having a bandwidth of only 5 GHz, integrated on a single SoC. The performance of the DAC will be evaluated by optical communication experiments with 200GBd, 16-QAM Nyquist signals (1.6 Tbit/s for polarization multiplexing) in a communication testbed. We aim to show the potential of this new signal processing method for communication networks with Tbit/s data rates. If successful, HighDAC will pave the way to fully integrated high-bandwidth DAC on a CMOS platform for communication networks, wireless devices and data centers of tomorrow. Besides communications, HighDAC will enable very high bandwidth arbitrary waveform generators for radar systems in autonomous driving, for sensors and measurement devices.

• DFG Programme: Research Grants