Project Details
Projekt
DRAMaOS: DRAM-aware OS
Subject Area
Security and Dependability, Operating-, Communication- and Distributed Systems
Computer Architecture, Embedded and Massively Parallel Systems
Computer Architecture, Embedded and Massively Parallel Systems
Term
since 2025
Project identifier
Deutsche Forschungsgemeinschaft (DFG) - Project number 567410490
The computer's main memory is arguably the most fundamental kind of memory the operating system (OS) has to manage for user processes, the IO subsystem, and the kernel itself. The memory page has become the de facto entity for all usages of main memory and even the access to disk files by via means of page-based file mappings. Treating all memory equally at page-frame granularity was the core idea for the elegance of the Mach memory model and is still the foundation of memory subsystems in all modern operating systems. On the hardware side, main memory is mostly provided by DRAM, for which advances in hardware density have made it possible to build systems with TiB of main memory. Internally, modern DRAM subsystems employ complex topologies with multiple channels or pseudo-channels distributing the memory and its accesses across ranks, bank groups, banks, and rows in order to improve the efficient wiring and therefore nonfunctional properties, such as access latency and throughput, energy consumption, robustness, and security. All these are influenced by the actual access and allocation patterns at runtime – all memory is not equal. A modern DRAM system is highly hierarchical, accesses to different addresses might have different behavior. In a sense, modern DRAM can be seen as a (small-scale) heterogeneous memory system (HMS) on its own. Upcoming standards, such as LPDDR6, DDR6, or HBM4, provide even more features to trade available memory, throughput, energy, and security, while new trends, such as CXL.mem, processing-in-memory (PIM), add new dimensions to the DRAM hierarchy. So far, most of this hierarchy is hidden from the OS behind the memory controller (MC). However, there is significant potential for optimization if the OS becomes DRAM-aware – and the MC OS-aware. Since the MC already requires detailed knowledge of the internal DRAM hierarchy to function correctly, it is ideally positioned to provide the OS with additional metadata about the memory system, and moreover, the OS could even delegate specific memory maintenance tasks to the controller itself. So far, most of this is hidden from the OS behind the memory controller (MC). However, there is significant potential for optimization if the OS becomes more DRAM-aware – and the MC more OS-aware. Since the MC already requires detailed knowledge of the internal DRAM hierarchy to function correctly, it is ideally positioned to provide the OS with information and control facilities about the memory system. Moreover, with a programmable "active" MC, the OS could even offload specific memory maintenance tasks, such as page zeroing or copying. In DRAMaOS, we investigate the OS–MC interface from both sides. We explore the potential of an OS–MC co-design approach to improve nonfunctional properties (such as energy consumption) of DRAM-intensive systems by adaptable DRAM-aware OS strategies and OS-aware MC functionality.
DFG Programme
Priority Programmes
Subproject of
SPP 2377:
Disruptive Main-Memory Technologies
