MS/s Extreme Resolution CT Incremental DS Converters - MegaExtReCTIC

• Applicant: Professor Dr.-Ing. Maurits Ortmanns
• Subject Area: Electronic Semiconductors, Components and Circuits, Integrated Systems, Sensor Technology, Theoretical Electrical Engineering
• Term: since 2025
• Project identifier: Deutsche Forschungsgemeinschaft (DFG) - Project number 568451019

There is an ever-increasing demand for high performance ADCs across all technology nodes for applications in industrial sensing, research instrumentation, communication, imaging and many more. ADCs in the extreme resolution range are largely limited in effective resolution, often having effective bit counts an order of magnitude below the claimed performance. In recent years, the multi-MS/s performance range with SNDR>100dB has been occupied by leading industry designs based on SAR ADCs in legacy (mostly 180nm) CMOS technology nodes. Their performance could only be achieved with very high input voltages of around 10Vpp. Huge sampling capacitors driven with extreme precision at such high input voltages and speeds consume enormous power, often more than one to two orders of magnitude higher than the ADC itself. To achieve (deep inband) 100-120dB linearity, such ADCs rely heavily on digital calibration, which consumes huge area in old technologies. However, linearity drops sharply by 1-2 orders of magnitude before the band edge, and peak performance is achieved only at deep in-band frequencies. There is currently no solution to overcome these shortcomings. This is the motivation for this project proposal. We perform architecture and circuit research to address these shortcomings of the state of the art. We combine our experience of achieving high linearity wideband continuous-time delta-sigma ADCs with our experience of intrinsically linear and dynamically reconfigurable incremental ADCs to realize a new group of extreme resolution converter architectures operating in the MS/s range and providing true Nyquist sample-to-sample conversion, which 1) has easy-to-drive continuous-time inputs, 2) eliminates the need for large sampling capacitors and their power-hungry drivers, as well as the frequency-dependent non-linearity of the sampling switch, 3) eliminates the need for area and power-hungry digital linearization, and 4) delivers extreme performance and linearity over the entire Nyquist band. 5) This new family of ADCs will also allow realization in scaled CMOS with core supply input voltages. The architectures will be based on continuous-time incremental ADCs, where we need to find architectures that achieve extreme resolution for low to moderate oversampling to keep sampling frequencies feasible, we need to work on calibration algorithms that operate in incremental mode. We also need to research feedback DAC linearization for both static and dynamic errors, where the state of the art does not provide solutions for wider bandwidth in incremental mode.

• DFG Programme: Research Grants