Project Details
Projekt
Experimental node-level energy efficiency analysis
Subject Area
Computer Architecture, Embedded and Massively Parallel Systems
Term
since 2026
Project identifier
Deutsche Forschungsgemeinschaft (DFG) - Project number 545776403
Within this project of the research unit Mod4Comp, we will improve the accuracy and quality of performance and energy-efficiency measurement and analysis for contemporary and advanced computing architectures. Modern computer architectures have become increasingly complex, including transistors being spent on concurrent processing capabilities, but also specialized computational resources, such as accelerators for various tasks. The latter typically speed-up the execution of the code they were designed for but also introduce additional synchronization overheads. To optimize the performance of programs, it is necessary to consider the various parameters of the hardware when scheduling computational tasks. While the architectural complexity increased with heterogeneity, processors and accelerators now also include more dynamic power-saving capabilities. While these can directly influence the power consumption of the hardware and therefore the energy-efficiency of the computation, they also influence the runtime, for example when the hardware performance is limited to stay within a given power budget. The complexity of the dynamic power-saving capabilities is further increased by the control mechanisms at hardware, operating system, and user-level, and the influence of noise, which can trigger the control mechanisms. The goal of this subproject is to gain and publish insight into the interaction of energy efficiency features of new architectures and their impact on performance. Such insight is crucial for understanding, modeling, and optimizing the energy efficiency and performance of systems and algorithms. The proposed research unit will leverage the gained insight within the Multi-layer Modeling module. To evaluate the energy efficiency of systems, we utilize a broad spectrum of available information. Architecture descriptions and the knowledge of typical mechanisms in contemporary architectures constitute a starting point but often lack quantitative details. To fill in the gaps, we built tools that stress specific components and monitor the influence on hard- and software. For this project, we will extend and use our tools to observe how a system behaves under specific conditions. Typical research questions addressed in this project include: 1) Can the system guarantee the specified core frequencies for a high-demanding workloads? 2) How precisely does the power limiting operate? For different power limits, different dynamic workloads, and different utilization of cores. 3) For what time frame can the TDP be exceeded? What is the temporal sequence with respect to power consumption and effective core frequency? For different core utilizations, different power excess, and a well-defined cooling configuration. 4) What is the practically achievable memory bandwidth? With respect to different points in the memory hierarchy, under different core/uncore frequencies, and for different NUMA configurations.
DFG Programme
Research Units
