Project Details
Projekt
Analytic chip-level performance, power, and energy modeling
Applicant
Dr. Georg Hager
Subject Area
Computer Architecture, Embedded and Massively Parallel Systems
Hardware Systems and Architectures for Information Technology and Artificial Intelligence, Quantum Engineering Systems
Hardware Systems and Architectures for Information Technology and Artificial Intelligence, Quantum Engineering Systems
Term
since 2026
Project identifier
Deutsche Forschungsgemeinschaft (DFG) - Project number 545776403
This project within the Mod4Comp Research Unit aims at providing comprehensive analytic, first-principles, gray- or white-box performance and power models for the node architectures under consideration. This includes standard multicore server CPUs, state-of-the-art high-performance GPGPUs, low-power embedded CPUs, and in-memory computing devices. First-principles analytic models for performance and power are simplified mathematical descriptions of hardware-software interactions, much along the lines of the well-known Roofline model. They require a machine model, which encodes all relevant features of the hardware, and an application model, which describes how the application uses the resources of the machine to solve the numerical problem at hand. Both are put together to arrive at predictions of resource usage, e.g., runtime or energy consumption. The great advantage of first-principles models is that they are built on assumptions about the features of the hardware-software interaction: If the model can be validated on existing hardware, one can be confident that it will also be useful for describing new hardware that does not exist yet. In the same vein, if the model cannot be validated, i.e., if its predictions are too far off the measurements, one can try to refine and improve it. Either way, valuable insights about the dominant bottlenecks and hot spots are gained. This project will refine and validate existing execution-cache-memory (ECM), communication, and power dissipation models. This will require extensive microbenchmarking and measurements for parameter fitting and validation, for which we rely on intense collaboration with SP1, SP5, SP6, and SP7 because these subprojects deal with actual measurements and/or unconventional hardware architectures. In terms of performance modeling, the set of architectures covered up to now will be greatly extended, shedding light on the role of overlapping and latency effects in the memory hierarchy on a wide spectrum of hardware platforms. The energy model previously developed by the group will be extended in two directions: The existing phenomenological power model will be extended to cover new hardware devices, and a microscopic model will be developed that aims at providing useful, quantitative predictions based on energy quanta for elementary operations. Both performance and energy models will be embedded in a well-defined methodology that can be adapted to future devices with limited effort. The refined models will immediately and continuously be integrated in the MPI simulator framework. As a further contribution to the tooling ecosystem, the subproject will extend the popular LIKWID tool suite to support external data sources to make it compatible with devices that do not allow easy user-level access to relevant performance and energy data.
DFG Programme
Research Units
