NaSCA: Nano-Scale Seitenkanalanalyse - Physikalische Sicherheit von CMOS ICs der nächstem Generation
Zusammenfassung der Projektergebnisse
The goal of this project was to evaluate and improve the physical security of cryptographic hardware implementations in cutting-edge semiconductor technology. This is an important objective due to the continually increasing number and importance of cyber-physical and security-sensitive embedded systems in our everyday life. Many different applications, including electronic identification with smart cards or phones for banking, traveling and access restriction, as well as security-enabled devices for automotive, medical, smart home and industrial automation purposes, rely on strong and robust cryptography implemented (primarily) in tiny and cheap pieces of hardware. The cryptographic implementations on such devices not only have to be mathematically secure, they also need to withstand attackers that gain physical access to the hardware and may observe its emissions during the execution of cryptographic protocols. One of the main sources of unintentional information leakage in such scenarios is the power consumption of computing devices. Whenever adversaries can measure the power consumption of a cryptographic device during the processing of secret material like cryptographic keys, it is possible to learn information about those secrets. It is well known that the down scaling of chip technology over the past decades has caused significant changes in the power consumption behavior of modern computing devices. In particular, while the dynamic power consumption per logic unit declines due to smaller capacitances and lower supply voltages, the static power consumption intensifies in newer technology generations due to lower threshold voltages, shorter channel lengths and thinner gate oxides. Due to these contrary trends it is required to shift at least a part of the focus from the dynamic power consumption to the static power consumption when evaluating the side-channel security of embedded devices in nanometer technologies. This project tried to make a first step in that direction by designing and manufacturing test chips in 90 nm, 65 nm, 40 nm and 28 nm CMOS technologies to evaluate them for their static power side-channel security. In the course of this project it was discovered that several characteristics of the static power consumption make it particularly dangerous as a source of information leakage. For instance, adversaries can significantly increase the information leakage through this side channel by increasing the supply voltage or the temperature of the device under test to figuratively squeeze the secrets out of the target. Furthermore, while traditional power analysis attacks can only learn information about secrets while they are actively processed by the hardware, this new form of adversary can extract information as long as it is present or saved anywhere in the circuit. Finally, it has been discovered that the inherent noise reduction of static power sidechannel attacks allows adversaries to circumvent countermeasures that rely on significant noise levels to be effective. Considering all these discoveries it is clearly necessary to develop dedicated protection mechanisms against this threat. In this project multiple combined masking and hiding countermeasures have been evaluated for their ability to prevent the extraction of secret information through the static power consumption from devices manufactured in advanced nanometer technologies. Those results will be helpful for the design of high-security cryptographic hardware in nanometer semiconductor technologies in the future.
Projektbezogene Publikationen (Auswahl)
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On the Easiness of Turning Higher-Order Leakages into First-Order. In S. Guilley, editor, Constructive Side-Channel Analysis and Secure Design - 8th International Workshop, COSADE 2017, Paris, France, April 13-14, 2017, Revised Selected Papers, volume 10348 of Lecture Notes in Computer Science, pages 153–170. Springer, 2017
T. Moos and A. Moradi
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Static Power Side-Channel Analysis of a Threshold Implementation Prototype Chip. In D. Atienza and G. D. Natale, editors, Design, Automation & Test in Europe Conference & Exhibition, DATE 2017, Lausanne, Switzerland, March 27-31, 2017, pages 1324–1329. IEEE, 2017
T. Moos, A. Moradi, and B. Richter
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Exploring the Effect of Device Aging on Static Power Analysis Attacks. IACR Trans. Cryptogr. Hardw. Embed. Syst., 2019(3):233–256, 2019
N. Karimi, T. Moos, and A. Moradi
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Glitch-Resistant Masking Revisited or Why Proofs in the Robust Probing Model are Needed. IACR Trans. Cryptogr. Hardw. Embed. Syst., 2019(2):256–292, 2019
T. Moos, A. Moradi, T. Schneider, and F. Standaert
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Static Power SCA of Sub-100 nm CMOS ASICs and the Insecurity of Masking Schemes in Low-Noise Environments. IACR Trans. Cryptogr. Hardw. Embed. Syst., 2019(3):202–232, 2019
T. Moos
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Side-Channel Hardware Trojan for Provably- Secure SCA-Protected Implementations. IEEE Trans. Very Large Scale Integr. Syst., 28(6):1435– 1448, 2020
S. Ghandali, T. Moos, A. Moradi, and C. Paar
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Static Power Side-Channel Analysis - An Investigation of Measurement Factors. IEEE Trans. Very Large Scale Integr. Syst., 28(2):376–389, 2020
T. Moos, A. Moradi, and B. Richter
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The Risk of Outsourcing: Hidden SCA Trojans in Third- Party IP-Cores Threaten Cryptographic ICs. In IEEE European Test Symposium, ETS 2020, Tallinn, Estonia, May 25-29, 2020, pages 1–6. IEEE, 2020
D. Knichel, T. Moos, and A. Moradi
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Unrolled Cryptography on Silicon - A Physical Security Analysis. IACR Trans. Cryptogr. Hardw. Embed. Syst., 2020(4):416–442, 2020
T. Moos
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Countermeasures against Static Power Attacks - Comparing Exhaustive Logic Balancing and Other Protection Schemes in 28 nm CMOS. IACR Trans. Cryptogr. Hardw. Embed. Syst., 2021(3), 2021
T. Moos and A. Moradi
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DL-LA: Deep Learning Leakage Assessment - A modern roadmap for SCA evaluations. IACR Trans. Cryptogr. Hardw. Embed. Syst., 2021(3), 2021
T. Moos, F. Wegener, and A. Moradi
