Optimum Capacitor Switching Algorithms For Successive Approximation Register (SAR) Analogue-to-Digital Converters (ADC)
Final Report Abstract
Modern Successive Approximation Analog to Digital Converter (SAR ADC) energy efficiency improvement techniques are very diverse. The majority of them concentrate on the order of the capacitor switching together with the specific interconnections in the switched capacitor digital to analog converter (DAC) in the feedback path. These methods have certain disadvantages when it comes to the application specific factors: extra energy loss on the reset, necessity to use precise voltage generators that consume extra power or the common-mode offset variation during conversion cycle that increases the comparator complexity. The input capacitance is another factor that plays a significant role in the system-level power budget but often goes unnoticed. This DFG research project was aimed to optimize SAR ADC energy efficiency taking the above factors into consideration. Alongside with the optimization, the further architectural improvements were designed. Given the SAR ADC building blocks specific, such as switched capacitor DAC, the idea of improving the switching procedure itself rather than structure and order is appealing. The optimal charging significantly reduces the energy required to charge a capacitor: up to two times for a single capacitor and up to 66% when applied to the 10-bit DAC matrix. Furthermore, since this method does not rely on the DAC’s switching order and interconnections, it becomes possible to use it together with the existing improvement techniques to further reduce power consumption. The optimal charging 10bit 1Ms/s SAR ADC was implemented on chip using UMC 65nm technology. The produced prototypes are fully functional and have ENOB of 9.2 and Walden FOM of 25fJ/conv. The power consumption, however, is more than expected. The reason seems to be implementation related rather than conceptual. Nevertheless, certain conceptual nuances were also found during the design process. The extra circuitry necessary for the optimal charging introduces the extra energy consumption. Therefore, the application of this technique is justified when the DAC switching energy savings are more than the extra power consumption introduced. For example, when the low-power digital library is available, or when the DAC resolution is more than 10 bit and design of the DAC matrix is mismatch-limited. In these cases, it is likely that digital part power consumption will be a minor part of the whole budget and the saved switching energy will exceed the introduced losses. Several new architectures were also designed and simulated during the work on the project. Two noiseshaping SAR ADC architectures that achieve higher accuracy by moving the noise to the right side of the spectrum, a pipeline SAR ADC with passive charge sharing and reduced sampling capacitance, the SAR ADC with DAC separation that significantly reduces the switching energy together with the sampling capacitance and the flying capacitor sampling technique that is aimed at reducing the sampling capacitance.
Publications
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Flying-Capacitor Bottom-Plate Sampling Scheme for Low-Power High-Resolution SAR ADCs, 2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC), 2018, pp. 1-4
D. Osipov & S. Paul
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First Order Fully Passive Noise-Shaping SAR ADC Architecture with NTF Zero close to One. 2019 17th IEEE International New Circuits and Systems Conference (NEWCAS) (2019, 6), 1-4. American Geophysical Union (AGU).
Osipov, Dmitry; Gusev, Aleksandr & Paul, Steffen
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Multi-step capacitor switching scheme for low-power SAR ADC. 2019 17th IEEE International New Circuits and Systems Conference (NEWCAS) (2019, 6), 1-4. American Geophysical Union (AGU).
Gusev, Aleksandr; Osipov, Dmitry & Paul, Steffen
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SAR ADC Architecture with Fully Passive Noise Shaping. 2019 IEEE 31st International Conference on Microelectronics (MIEL) (2019, 9), 219-222. American Geophysical Union (AGU).
Osipov, D.; Gusev, A.; Shumikhin, V. & Paul, St.
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Two-Step Pipeline SAR ADC with passive Charge Sharing between Cascades. 2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) (2019, 10), 8138-8143. American Geophysical Union (AGU).
Osipov, Dmitry; Gusev, Aleksandr; Paul, Steffen & Shumikhin, Vitaly
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An Energy Efficient SAR ADC Architecture with DAC Separation. 2020 18th IEEE International New Circuits and Systems Conference (NEWCAS) (2020, 6), 118-121. American Geophysical Union (AGU).
Gusev, Aleksandr; Osipov, Dmitry & Paul, Steffen
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Noise shaping in SAR ADC. Facta universitatis - series: Electronics and Energetics, 33(1), 15-26.
Osipov, Dmitry; Gusev, Aleksandr; Shumikhin, Vitaly & Paul, Steffen
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By Design Correction of Capacitors Mismatch in SAR ADC with Split Capacitor DAC. 2021 IEEE 32nd International Conference on Microelectronics (MIEL) (2021, 9, 12), 209-212. American Geophysical Union (AGU).
Osipov, D.; Guscv, A. & Paul, S.
