Modeling-Technology Co-Optimization of the oxide/silicon interface for cryogenic applications of MOSFETs

• Applicants: Professor Dr.-Ing. Christoph Jungemann; Professor Dr. Joachim Knoch
• Subject Area: Electronic Semiconductors, Components and Circuits, Integrated Systems, Sensor Technology, Theoretical Electrical Engineering
• Term: since 2026
• Project identifier: Deutsche Forschungsgemeinschaft (DFG) - Project number 572684796

Semiconductor spin qubits are promising for the realization of quantum computers but require very low temperatures and complex control electronics. In the case of a few qubits the control electronics can be placed outside of the cryostat, but in the case of a hundred or more qubits the control electronics have to be placed in the cryostat to reduce the heat flow and volume of the interconnects. Thus, the control electronics have to be operated at 4.2 K or below. Hence, for the design of cryogenic circuits accurate simulation models are required. This has led to a renewed interest in characterization and modeling of electron and hole transport in silicon MOSFETs at cryogenic temperatures. Since the cooling capacity is very limited at cryogenic temperatures, heat dissipation by the control electronics should be as low as possible. The power consumption of the control electronics can be reduced by operating the MOSFETs in the subthreshold regime where the current depends exponentially on changes in the gate bias which is characterized by the subthreshold swing, that is proportional to the temperature at 300K. By lowering the temperature, the subthreshold swing can be reduced and thus the power consumption. At 4.2K the ideal subthreshold swing should be about 0.84mV/dec, but it turns out that due to band tailing and traps the subthreshold swing saturates at cryogenic temperatures at a significantly higher value. In addition, inflection of the drain current occurs. Both phenomena are due to disorder at the interface between the oxide and silicon which results in potential fluctuations degrading the transistor performance. For further optimization of cryogenic MOSFETs a better understanding of the oxide/semiconductor interface is required. While there is often a rather independent development of experimental and modeling work, in the present project we aim at a modeling-technology co-optimization. This means, that the choice of experimental devices, their dimensioning, the used fabrication processes as well as the measurements will be designed jointly by the project partners in order to ensure that the experimental data serves the needs for proper model development and verification. We will fabricate MOS-capacitors, MOSFETs an Hall bar structures on the same chip to study the subthreshold swing, band tailing, trap densities at the interface and the low-field drift mobility of electrons and holes in the channel of the MOSFETs. This will be done for various gate stacks to investigate the impact of disorder at the MOS interface on the electronic transport in the devices‘ on- and off-state. In addition, we will fabricate bulk MOSFETs with different bulk doping concentration as well as SOI transistors and carry out comprehensive device modeling including the measurement process. The results of the modeling will be used to explain the observed phenomena and to optimize the next generation of devices whose experimental data will be used for model refinement.

• DFG Programme: Research Grants