Project Details
Projekt
MOdelling and Simulating In-memory Computing on chip and node level (MOSIC)
Applicant
Professor Dr.-Ing. Dietmar Fey
Subject Area
Computer Architecture, Embedded and Massively Parallel Systems
Term
since 2026
Project identifier
Deutsche Forschungsgemeinschaft (DFG) - Project number 545776403
The project MOSIC takes on modelling at chip and node level within the research unit MOD4COMP, which is working on a new holistic approach to predicting energy and performance in computing systems by means of modelling, ranging from chip to node and to network level. The aim of MOSIC's research on modelling is to map the use of new non-volatile memory (NVM) technologies, e.g. ReRAMs and ferroelectric devices, which offer a noticeable reduction in power requirements at the chip and node level. This will be achieved mainly through two architecture measures: (i) New in-memory computing (IMC) instructions that avoid the energy-intensive data transport from memory to processor by low-energy instructions to be executed in or near at memory. (ii) The use of so-called hybrid memories that couple conventional memory (DRAM or SRAM) with NVM serving as a back-up. This enables temporary, energy-saving switching off of the processor and energetically favourable data reading. These qualitative advantages must be quantitatively evaluated along the entire memory hierarchy, from registers to cache levels to main memory. Furthermore, it must be checked which operations are suitable for an IMC instruction at which location in the memory hierarchy. For this, suitable models for NVMs are needed, which capture IMC and hybrid memories appropriately. Such models do not exist yet, because existing models for NVMs are too physically oriented and unsuitable for the system level investigations due to too high simulation times, or they abstract too much and only model functional but no non-functional properties, such as computing time, access time and energy demand. In MOSIC, new architecture models that include runtime and power requirements for IMC operations and accesses to hybrid memories are extracted from extended physical models through simulation. These architecture models are incorporated into processor simulators in order to prove and support the favourable use of NVMs at chip and node level in the sense of energy-saving sustainable computing when designing algorithms and architectures. In order for this proof to succeed, a new cycle-approximating processor simulator at node level is being designed in MOSIC, which uses analytical models from SP2 and SP3 and machine learning methods to be developed in MOSIC for energy and runtime prediction. Using the measurement methods from SP6 and SP7, the models and the new simulator are verified on real hardware. Using the architectural models and simulators from other SPs at higher levels, holistic assessments can be carried out with other subprojects with regard to sustainable computing for brain simulations with HPC resources (SP4), embedded HPC for video processing (SP7), e.g for autonomous driving, and for saving energy neuromorphic computing architectures with IMC (SP6).
DFG Programme
Research Units
