TRR 404:  Next Generation Electronics with Active Devices in Three Dimensions (Active-3D)

• Subject Area: Computer Science, Systems and Electrical Engineering
• Term: since 2025
• Website: Homepage
• Project identifier: Deutsche Forschungsgemeinschaft (DFG) - Project number 528378584

Semiconductor technology is the core of nearly all products and services of our society. This success was possible by ever smaller, cheaper, and less power consuming devices that make up integrated circuits and systems. The reduction of the physical size of the transistor resulted in lower cost per function, higher performance and strongly improved energy efficiency. However, in recent years the actual size of a transistor did not significantly scale any further. Instead, the continuation of Moore’s Law has been made possible by eliminating dead area utilizing new device architectures in a technology/circuit co-design. With novel 3D transistors improvements along the lines of Moore’s Law are expected. Heterogeneous system integration has been launched recently, where several chips/chiplets are combined in one package. However, all these developments increase the usable area of a chip, either by reducing dead space in between devices and/or enlarging the chip size, and therefore do not address the major road-block: the power consumption. The increasingly pervasive use of Machine Learning (ML) and Artificial Intelligence (AI) comes with an exponential increase of power consumption and the spatial separation of memory and logic across the area of today’s chips leads to the so-called “von Neumann bottleneck”. This TRR will utilize the volume on top of the chip area by integrating active devices into the Back-End of Line (BEOL) enabling logic and memory functionality as well as active interconnects. To this end, novel devices based on new and unconventional materials fabricated with low-thermal budget techniques will be developed and integrated into novel circuits and systems promising unprecedented improvements regarding the key performance indicators power, performance and area. Our materials/technology/circuit co-design approach provides an almost unlimited number of possibilities to arrange circuit functionalities across the BEOL volume allowing to exploit the fact that “there’s plenty of room on top” of the chip to its full extend. The realization of such an active BEOL requires the integration and tailoring of a large set of different materials, it needs highly sophisticated manufacturing technologies, an in-depth understanding of the interaction between materials, their processing and resulting device characteristics as well as a completely fresh way of looking at circuit and system design. To accomplish this, the TRR teams up inter-nationally renowned experts from Dresden and Aachen, starting from the quantum chemical material science aspects to novel electronic devices to discovering new circuit topologies and electronic systems. In addition, both sites bring along a top notch micro- and nanofabrication infrastructure. With the TRR “Next Generation Electronics with Active Devices in Three Dimensions” (Active-3D), Germany and, therefore, also Europe will be strengthened at the basic research level of microelectronics.

• DFG Programme: CRC/Transregios

Current projects

• A01 - Co-design of Area-Dependent VCM Cell Arrays and CMOS Circuits for In-Memory Com-puting (Project Heads Dittmann, Regina ;  Slesazeck, Stefan )
• A02 - Under Voltage Control: Nb2O5 Based Locally Active Threshold Switches (Project Heads Slesazeck, Stefan ;  Tetzlaff, Ronald )
• A03 - 3D Integration of Tailored Phase-Change Memories (PCMs) (Project Heads Ingebrandt, Sven ;  Wuttig, Matthias )
• A04 - 3D Racetrack Memory Devices (Project Heads Parkin, Stuart ;  Rellinghaus, Bernd )
• A05 - BEOL-Compatible 3D Reconfigurable Logic (Project Heads Knoch, Joachim ;  Trommer, Jens )
• A06 - 2D Field-Effect Transistors (Project Heads Feng, Xinliang ;  Lemme, Max Christian )
• A07 - Vertical Perovskite Field-Effect Transistors (Project Heads Mohammadi, Ph.D., Maryam ;  Vaynzof, Yana )
• B01 - ECM-Type Devices as 3D Programmable Interconnects (Project Heads Knoch, Joachim ;  Valov, Ilia )
• B02 - 1T1R – 2D-FET and VCM-Device BEOL Integration (Project Heads Hoffmann-Eifert, Susanne ;  Wang, Zhenxing )
• B03 - Reliability Assessment (Project Head Max, Benjamin )
• B04 - Analog Computing Circuits Exploiting Devices Integrated into the BEOL (Project Head Negra, Renato )
• B05 - Joint Logic, Memory, and Routing Synthesis (Project Heads Gemmeke, Tobias ;  Kumar, Akash )
• B06 - System Models, Architectures, and Application Mapping Tools (Project Heads Castrillon-Mazo, Jeronimo ;  Leupers, Ph.D., Rainer )
• B07 - Reconfigurable Architecture (Project Heads Gemmeke, Tobias ;  Goehringer, Diana )
• C01 - 3D Architecture Schemes and Processes (Project Heads Lemme, Max Christian ;  Mikolajick, Thomas )
• C02 - Hierarchical Device Simulation and Modeling (Project Heads Jungemann, Christoph ;  Menzel, Stephan )
• C03 - Materials at Work – Characterization of Devices Under Operating Conditions (Project Heads Dittmann, Regina ;  Rellinghaus, Bernd )
• MGK - Integrated Research Training Group (Project Heads Dittmann, Regina ;  Goehringer, Diana ;  Ingebrandt, Sven )
• Z - Central Tasks of the TRR (Project Head Mikolajick, Thomas )

• Applicant Institution: Technische Universität Dresden
• Co-Applicant Institution: Rheinisch-Westfälische Technische Hochschule Aachen
• Participating Institution: AMO GmbH; Gesellschaft für Angewandte Mikro- und Optoelektronik mbH; Forschungszentrum Jülich; Max-Planck-Institut für Mikrostrukturphysik; NaMLab gGmbH
• Participating University: Ruhr-Universität Bochum
• Spokesperson: Professor Dr.-Ing. Thomas Mikolajick